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corepwm v4.1 handbook
actel corporation, mountain view, ca 94043 ? 2010 actel corporation. all rights reserved. printed in the united states of america part number: 50200113-2 release: february 2010 no part of this document may be copied or reproduced in any form or by any means without prior written consent of actel. actel makes no warranties with respect to this do cumentation and disclaims any implied warranties of merchantability or fitness for a particular purpose. information in this document is subject to change without notice. actel assumes no responsibility for any errors that may appear in this document. this document contains confidential proprietary information that is not to be disclosed to any unauthorized person without prior written consent of actel corporation. trademarks actel, igloo, actel fusion, proasic, libero, pigeon point and the associated logos are trademarks or registered trademarks of actel corporation. all other trademarks and service marks are the property of their respective owners.
3 table of contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 core overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 supported families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 core version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 supported interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 utilization and performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1 design description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 apb interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2 tool flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 smartdesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 importing into libero ide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 simulation flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 synthesis in the libero ide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 place-and-route in libero ide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3 example applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 general purpose pwm application C temperature monitor . . . . . . . . . . . . . . . . . . . 29 dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4 software driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 a list of document changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 b product support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 customer service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 actel customer technical support center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 actel technical support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 contacting the customer technical support center . . . . . . . . . . . . . . . . . . . . . . . . 37 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5 introduction core overview intended use corepwm is a general purpose, multi-channel pulse wi dth modulator (pwm) module for motor control, tone generation, battery charging, heating elements, and more. in general purpose pwm mode, duty cycle updates can be performed asynchronously or synchronously, based on parameter selection. in synchronous mo de, all channels are updated at the be ginning of the pwm period, which is useful for motor control and can be used to keep a constant dead band space between channel waveforms. asynchronous mode is relevant to applications such as led control, wh ere synchronous updates are not required. asynchronous mode lowers the area size, reducing shadow register requirements. in addition to the general purpose pwm modes, there is a "low ripple dac" mode that creates a minimum period pulse train whose high/low average is that of the chosen duty cycle. when used with a low-pass filter (such as a simple rc circuit), a dac can be created with far better bandwi dth and ripple performance than a standard pwm algorithm can achieve. this type of dac is ideally suited for fine tuning of power supply output levels. corepwm also provides suppport for tachom eter monitoring of 3- and 4-wire fans . incoming tachometer data is read by the firmware through the apb interface to calculate fan speed. key features ? configuration updates for all channels can be synchronized to the beginnin g of the pwm period, allowing precise updates and maintaining phase alignments between channels ? configurable resolution based on the apb bus width ? low-cost pwm solution with up to 16 separate pwm di gital outputs, configurable via a register interface ? for dac applications: optional, per-channel low ripple dac mode, allowing for greater resolution output of a given filter ? low-cost tachometer solution with up to 16 separate tach digital inputs, configurable via a register interface ? all pwm outputs are double-edge-controlled ? per-channel fixed register option for lower tile count ? edge control based on a configurable pwm period with prescaler value and 0% to 100% duty cycle capability ? set high, set low, and toggle edge-control modes ? can be programmed on-the-fly from a microcontroller, such as core8051s, coreabc ? can be used to perform open or cl osed-loop margining of power supplies supported families ?igloo?/e ? proasic?3/e/l ?fusion ?proasic plus ? ?axcelerator? ?rtax-s ?rtax-dsp
introduction corepwm v4.1 6 core version this handbook supports corepwm version 4.1. supported interfaces corepwm is available with an apb in terface, which is described in the apb interface timing section on page 24 . utilization and performance corepwm has been implemented in several of actels device families. a summary of various implementation data is listed in the following tables (using standard speed grades). as shown in table 1 through table 8 on page 9 , it is recommended to fix all registers that are not used, via parameters, to ensure optimal synthesis tile reduction. table 1 corepwm device utilization and performance (one 8-bit dac channel configuration) family tiles utilization performance (mhz) sequential combinatorial total device total igloo?/e 20 96 116 agle600 1.0% 72 proasic?3/e 20 76 96 a3p250 2.0% 96 fusion 20 76 96 afs600 1.0% 101 proasic plus ? 20 102 122 apa300 1.0% 101 axcelerator? 20 31 51 ax250 1.0% 252 rtax-s 20 31 51 rtax250s 1.0% 223 note: data in this table were achieved using typical synthesis and layout settings. top-level parameters/generics were set as follows: pwm_num = 1, apb_dwidth = 8; dac_mode 1 = 1 (dac mode), fixed_prescale_en = 1, fixed_prescale = 0, fixed_period_en = 1, fixed_period = 1, shadow_reg_en1 = 0. table 2 corepwm device utilization and performance (one 16-bit dac ch annel configuration) family tiles utilization performance (mhz) sequential combinatorial total device total igloo/e 54 147 201 agle600v2 2.0% 59 proasic3/e 54 111 165 a3p250 3.0% 85 fusion 54 111 165 afs600 1.0% 94 proasic plus 55 209 264 apa200 3.0% 74 note: data in this table were achieved using typical synthesis and layout settings. top-level parameters/generics were set as follows: pwm_num = 1, apb_dwidth = 16; dac_mode1 = 1 (dac mode), fixed_prescale_en = 1, fixed_prescale = 0, fixed_period_en = 1, fixed_period = 1, shadow_reg_en1 = 1.
corepwm v4.1 utilization and performance 7 axcelerator 57 53 110 ax250 2.0% 210 rtax-s 57 53 110 rtax250s 1.0% 176 table 3 corepwm device utilization and performance (one 8-bit general purpose pwm channel configuration) family tiles utilization performance (mhz) sequential combinatorial total device total igloo/e 15 55 70 agle600v2 1.0% 82 proasic3/e 15 55 70 a3p250 1.0% 130 fusion 15 55 70 afs600 1.0% 144 proasic plus 15 58 73 apa300 1.0% 141 axcelerator 16 40 56 ax250 1.0% 181 rtax-s 16 40 56 rtax250s 1.0% 187 note: data in this table were achieved using typical synthesis and la yout settings. top-level parameters/generics were set as follows : pwm_num = 1, apb_dwidth = 8; dac_mode1 = 0 (general purpose pwm mode) , fixed_prescale_en = 1, fixed_prescale = 0, fixed_period_en = 1, fixed_period = 8, fixed_pwm_pos_en1 = 1, fixed_pwm_posedge1 = 0, fixed_pwm_ne g_en1 = 0, fixed_pwm_negedge1 = 0, shadow_reg_en1 = 0 table 4 corepwm device utilization and performance (one 16-bit general purpose pwm channel configuration) family tiles utilization performance (mhz) sequential combinatorial total device total igloo/e 91 272 363 agle600v2 3.0% 46 proasic3/e 91 275 366 a3p250 6.0% 72 fusion 91 275 366 afs600 3.0% 79 proasic plus 127 482 609 apa300 6.0% 59 axcelerator 93 145 238 ax250 6.0% 110 rtax-s 93 145 238 rtax250s 6.0% 88 note: data in this table were achieved using typical synthesis and la yout settings. top-level parameters/generics were set as follows : pwm_num = 1, apb_dwidth = 16; dac_mode1 = 0 (general purpose pwm mode); shadow_reg_en1 = 1 , fixed_prescale_en = 1, fixed_prescale = 64. table 2 corepwm device utilization and performance (one 16-bit dac channel configuration) (continued) note: data in this table were achieved using typical synthesis and layout settings. top-level parameters/generics were set as follows: pwm_num = 1, apb_dwidth = 16; dac_mode1 = 1 (dac mode), fixed_prescale_en = 1, fixed_prescale = 0, fixed_period_en = 1, fixed_period = 1, shadow_reg_en1 = 1.
introduction corepwm v4.1 8 table 5 corepwm device utilization and performance (8-bit multiple-output configuration example: 3 dac mode outputs without shadow update register) family tiles utilization sequential combinatorial total device total performance (mhz) igloo/e 58 208 266 agle600v2 2.0% 76 proasic3/e 58 150 208 a3p250 3.0% 101 fusion 58 150 208 afs600 2.0% 109 proasic plus 58 280 338 apa300 4.0% 101 axcelerator 58 66 124 ax250 2.0% 250 rtax-s 58 66 124 rtax250s 2.0% 217 note: data in this table were achieved using typical synthesis and layout settings. top-level parameters/generics were set as follows: pwm_num = 3, apb_dwidth = 8; dac_mode1, dac_mode2, and dac_mode3 = 1 (dac mode) fixed_period_en = 1, fixed_period = 1, fixed_prescale_en = 1, fixed_prescale = 0, shadow_reg_en1 = 0, shadow_reg_en2 = 0, shadow_reg_en3 = 0. table 6 corepwm device utilization and performanc e (12-bit multiple-output configuration example: 3 dac mode outputs, 3 genera l purpose pwm mode outputs) family tiles utilization performance (mhz) sequential combinatorial total device total igloo/e 212 723 935 agle600v2 7.0% 45 proasic3/e 212 694 906 a3p250 15.0% 74 fusion 212 694 906 afs600 7.0% 82 proasic plus 229 1054 1,283 apa300 16.0% 67 axcelerator 216 307 523 ax250 12.0% 103 rtax-s 216 307 523 rtax250s 12.0% 87 note: data in this table were achieved using typical synthesis and layout settings. top-level parameters/generics were set as follows: pwm_num = 6, apb_dwidth = 16; dac_mode1, dac_mode2, and dac_mode3 = 1 (dac mode), dac_mode4, dac_mode5, and dac_ mode6 = 0 (general purpose pwm mode), fixed_prescale_en = 1, fixed_prescale = 8, shadow_reg_en1 = 0, shadow_reg_en2 = 0, shadow_reg_en3 = 0, shadow_reg_en3 = 0, shadow_reg_en4 = 0, shadow_reg_en5 = 0, shadow_reg_en6 = 0,.
corepwm v4.1 utilization and performance 9 table 7 corepwm device utilization and performance (one 16-bit general purpose pwm channel and one tach input configuration) family tiles utilization performance (mhz) sequential combinatorial total device total igloo/e 314 768 082 agle600v2 8.0% 47 proasic3/e 314 768 082 a3p250 18.0% 75 fusion 314 768 1,082 af600 8.0% 83 proasic plus 328 1,043 1,371 apa300 17.0% 70 axcelerator 319 483 802 ax250 19.0% 103 rtax-s 319 483 802 rtax250s 19.0% 87 note: data in this table were achieved using typical synthesis and layout settings. top-level parameters/generics were set as follows: config_mode = 1, pwm_num=3, tach_num=3,apb_dwidth=16; dac_mode1=0 (general purpose pwm mode), fixed_ prescale_en=1, fixed_prescale=8, fixed_period_en=0, fixed_pwm_pos_en1=1, fixed_pwm_posedge1=0, fixed_pwm_neg_en1=0, fixed_pwm_ negedge1=0, shadow_reg_en1=0, fixed_pwm_pos_en2=1, fixed_pwm_po sedge2=0, fixed_pwm_neg_en2=0, fixed_pwm_negedge2=0, shadow_reg_en2=0, fixed_pwm_pos_en3=1, fixed_pwm_posedge3=0, fixed_pwm_neg_en3=0, fixed_pwm_negedge3=0, shadow_reg_en3=0 table 8 corepwm device utilization and performance (one tach input cpnfiguration with 16-bit apb data width) family tiles utilization performance (mhz) sequential combinatorial total device total igloo/e 207 389 596 agle600v2 4.0% 52 proasic3/e 207 383 590 a3p250 10.0% 89 fusion 207 383 590 af600 4.0% 98 proasic plus 207 506 713 apa300 9.0% 92 axcelerator 209 269 478 ax250 5% 114 rtax-s 209 269 478 rtax250s 11% 101 note: data in this table were achieved using typical synthesis and layout settings. top-level parameters/generics were set as follows: config_mode = 2, tach_num=3, apb_dwidth=16.

11 1 design description functional blocks the corepwm (pulse width modulation) macro generates up to 16 general purpose pw m signals, as shown in figure 1-1 . corepwm includes a register interface block, ti mebase generation block, tack inf block, and pwm generation block. the register interface block connects to an apb bus for pwm register configuration and updating . descriptions for all registers are given in table 1-3 on page 15 . a shadow register may be used so that pwm waveform updates occur only at the beginning of a pwm period. a shadow register holds all values and writes them when the sync_update register is set to 1. in other words, for all channel synchronous updates, write a "1" to the sync_update register after writting to all the channel registers. the timebase generation block accepts prescale and period regist er values and produces a period count. the number of system clocks between period counts is equal to the prescale value. the pwm waveform generation block has two modes: general purpose pwm mode takes input period_cnt counter values and compares them with the register values for all the pwm positive and negative edge locations. when a co mparison is met, each respective output waveform is set to the correct high/low/toggle value. an example general purpose pwm waveform configuration is demonstrated in figure 1-3 on page 21 . the example explains the relationship between the prescale and period register values, and how to configure the pwm waveforms with a given prescale/period timebase. low ripple dac mode is intended to drive a low-pass filter, typically a single-pole rc filter. narrow pulses of constant width are spread evenly over time such that the average voltage is equal to the duty cycle. the output of the filter is then a dc voltage directly proportional to the duty cycle. this type of pulse train allows for much lower ripple at the output of the filter, and benefits from either higher bandwidth and/or smaller r and c values. in the tach interface module, the width of the decrementing counter is configured to 16 bits. the tach interface module is used to measure the period of the tachin[x] signal by measuring between two successive positive or negative edges of tachin[x]. the measured value will be stored in the corresponding inputs tachpulsedur register. the measured value will be read by the firmware through the apb interface. the access to the control and status registers of the tach interface module is through the apb interface. th e stored value in tachpulsedur will correspond to the count for half of a revolution of a four pole fan. when determining the speed for other than four pole fans, the algorithm figure 1-1 corepwm block diagram corepwm apb i/f pwm[pwm_num:1] tachin[tach_num-1:0] register interface timebase generation pwm waveform generation tach inf tachint
design description corepwm v4.1 12 that converts the counter value to rpms must be adjusted by the firmware. tach inf supports 16- and 32-bit apb interface, but it does not support 8-bit interfaces. to accurately measure the speed of 3-wire fans, you must turn on the fan periodically and long enough to get a complete tach measurement, often referred to as pwm pulse stretching. the pwm_stretch register allows you to set the desired pwmx signals to the level sp ecified by pwm_stretch_value. the following algorithm can be used to measure the speed of 3-wire fans. this algorithm assumes that the tachmodey bit is set to 1 (one-shot mode): ? software enables pulse stretching by writing a 1 to pwm_stretchx, which forces pwmx to pwm_stretch_valuex. this requirement is not enforced by the hardware. ? software can add a delay to ensure the fan tachometer circuitry is operational before enabling fan speed measurement. ? software clears the tachstatusy bit, enabling a one-time tach measurement on the input signal tachiny corresponding to one of th e fans controlled by pwmx ? software receives an interrupt and verifies that the tach measurement for tachiny has been completed (via tac h s tat u s y b i t ) ? software disables pulse stretching by writing a 0 to pwm_stretchx. i/o signals the port signals for the co repwm macro are defined in table 1-1 on page 13 and illustrated in figure 1-2 . all signals are either input (input only) or output (output only). figure 1-2 corepwm i/o signal diagram presetn pclk psel penable pwrite paddr[7:0] pwdata[apb_dwidth-1:0] pready pslevrr prdata[apb_dwidth-1:0] tachin[tach_num-1:0] pwm[pwm_num:1] tachint corepwm
corepwm v4.1 i/o signals 13 table 1-1 corepwm i/o signal descriptions name type description system signals presetn input active low asynchronous reset pclk input system clock C all operations and status shall be synchronous to the rising edge of this clock signal microcontroller signals psel input select line for corepwm penable input read output enable pwrite input write enable paddr[7:0] input register address pwdata[apb_dwidth-1:0] input write address/data input pready output ready signal, tied high pslverr output transfer error signal, tied low prdata[apb_dwidth-1:0] output read data output pwm signals pwm[pwm_num:1] output pulse width modulation output tach signals tachin[tach_num -1:0] input tach input tachint output interrupt output for the tachometer. this signal indicates a tachstatus register bit has been set to one. the polarity of this sign al is controlled by the tachint_act_level configurable option. note: all signals active-high (logic 1) unless otherwise noted.
design description corepwm v4.1 14 verilog/vhdl parameters corepwm has parameters (verilog) and generics (v hdl) for configuring the rtl code, described in table 1-2 . all parameters and generics are integer types. table 1-2 corepwm parameters/generics descriptions name description config_mode when 0, supports pwm only (legacy with dead banding support) when 1, supports both pwm and tach when 2, supports tach only pwm_num number of pwm outputs from 1 to 16. this parameter is used only when config_mode is set to 0 or 1. apb_dwidth pwm resolution and apb bus width from 8 to 32. this parameter must be set to either 16 or 32 when config_mode is either 1 or 2. fixed_prescale_en fixed prescale enable. fixed_prescale_en hardwires the register, disallowing apb write-access, and reducing tile count. this parameter is used only when config_mode set to 0 or 1. fixed_prescale hardwired prescale[apb_dwidth -1:0] register value. this parameter is used only when config_mode set to 0 or 1. fixed_period_en fixed period enable. fixed_period_en hardwires the register, disallowing apb write-access, and reducing tile count. this parameter is us ed only when config_mode set to 0 or 1. fixed_period hardwired period[apb_dwidth -1:0] register value. this parameter is used only when config_mode set to 0 or 1. shadow_reg_en x shadow register enable. synchronizes all register modification changes to the beginning of the pwm cycle; that is, when period count = 0. this parameter is used only when config_mode set to 0 or 1. dac_mode x dac mode. 1 = low ripple dac mode; 0 = general purpose pwm mode. note: x refers to each channel, from 1 to 16. this parameter is used only when config_mode set to 0 or 1. fixed_pwm_pos_en x fixed per channel positive edge enable. note: x refers to each channel, from 1 to 16. fixed_pwm_pos_en x hardwires the register, disallowing apb write-access, and reducing tile count. in a typical pwm application, either the fixed_pwm_pos_en x or the fixed_pwm_neg_en x could be set if one of those edges do not need to be software controlled with apb write-accesses. fixing both edges would result in static output. this parameter is used only when config_mode set to 0 or 1. fixed_pwm_posedge x hardwired posedge[apb_dwidth -1:0] register value. note: x refers to each channel, from 1 to 16. this parameter is used only when config_mode set to 0 or 1.
corepwm v4.1 register map 15 register map all registers are based on apb width parameter selection; default is 8 bits. fixed_pwm_neg_en x fixed_dac_out_enx fixed per channel negative edge enable. note: x refers to each channel, from 1 to 16. fixed_pwm_neg_en x hardwires the register, disallowing apb write-access, and reducing tile count. in a typical pwm application, either the fixed_pwm_neg_en x or the fixed_pwm_pos_en x could be set if one of those edges do not need to be software-controlled with apb write-accesses. fixing both edges would result in static output. for dac applications, the fixed_pwm_po s_enx value is unconnected while the fixed_dac_out_en x value would typically be disabled, as using it would result in static output. this parameter is used only when config_mode set to 0 or 1. fixed_pwm_negedge x fixed_dac_leveloutx hardwired negedge[apb_dwidth -1:0] register value. when in dac mode, this parameter also fixes dacx_levelout, which is typically not fixed in dac applications, as it would only create a static duty cycle output. note: x refers to each channel, from 1 to 16. this parameter is used only when config_mode set to 0 or 1. pwm_stretch_valuex defines pwmx level when pwm_stretchx is set to 1. when 0, pwmx is set to 0 if pwm_stretchx is set to 1; when 1, pwmx is set to 1 if pwm_stretchx is set to 1 (default). this parameter is used only when config_mode set to either 1 or 2. tac h _ n u m number of tachometer inputs from 1 to 16. this parameter is used only when config_mode set to 1 or 2. tac h _ ed g e y fixed per tachometer input edge select. selects the edge used to capture the counter value for the tach[x] input signals. 0, capture counter value on falling edge of tach[x] (default); 1, capture counter value on rising edge of tach[x]. this parameter is used only when config_mode set to 1 or 2. tachint_act_level selects active low or active high tachint interrupt: 0, active low interrupt (default); 1, active high interrupt. this parameter is used only when config_mode set to 1 or 2. table 1-2 corepwm parameters/generics descriptions table 1-3 corepwm register definitions register name paddr[7:0] description type default prescale 0x00 pwm mode: the system clock cycle is multiplied with the prescale value resulting in the minimum period count timebase. dac mode: the prescale and period registers could be used in conjunction with the shadow register to synchronize dac levelout. r/w 0x08 period 0x04 pwm mode: the prescale value is multiplied with the period value yielding the pwm waveform cycle. r/w 0x08 pwm_enable_0_7 0x08 bitwise channel enables for pwm/dac channels 1 through 8. r/w 0x00 pwm_enable_8_15 0x0c bitwise channel enables for pwm/dac channels 9 through 16. r/w 0x00
design description corepwm v4.1 16 sync_update 0xe4 sync_update: when this bit is set to "1" and shadow_reg_en is selected, all posedge and negedge registers are updated synchronously. synchronous updates to the pwm waveform occur only when shadow_reg_en is asserted and sync_update is set to 1. when this bit is set to "0", all the posedge and negedge registers are updated asynchronously. r/w 0x00 pwm1_posedge 0x10 pwm mode: sets the positive edge of the output with respect to the period resolution. when apb writes to this register, all the channels are updated. r/w 0x00 pwm1_negedge dac1_levelout 0x14 pwm mode: sets the negative edge of the output with respect to the period resolution. dac mode : sets the desired output level, from 0-100%. r/w 0x00 pwm2_posedge 0x18 pwm mode: sets the positive edge of the output with respect to the period resolution. r/w 0x00 pwm2_negedge dac2_levelout 0x1c pwm mode: sets the negative edge of the output with respect to the period resolution. dac mode : sets the desired output level, from 0-100%. r/w 0x00 pwm3_posedge 0x20 pwm mode: sets the positive edge of the output with respect to the period resolution. r/w 0x00 pwm3_negedge dac3_levelout 0x24 pwm mode: sets the negative edge of the output with respect to the period resolution. dac mode : sets the desired output level, from 0-100%. r/w 0x00 pwm4_posedge 0x28 pwm mode: sets the positive edge of the output with respect to the period resolution. r/w 0x00 pwm4_negedge dac4_levelout 0x2c pwm mode: sets the negative edge of the output with respect to the period resolution. dac mode : sets the desired output level, from 0-100%. r/w 0x00 pwm5_posedge 0x30 pwm mode: sets the positive edge of the output with respect to the period resolution. r/w 0x00 pwm5_negedge dac5_levelout 0x34 pwm mode: sets the negative edge of the output with respect to the period resolution. dac mode : sets the desired output level, from 0-100%. r/w 0x00 pwm6_posedge 0x38 pwm mode: sets the positive edge of the output with respect to the period resolution. r/w 0x00 pwm6_negedge dac6_levelout 0x3c pwm mode: sets the negative edge of the output with respect to the period resolution. dac mode : sets the desired output level, from 0-100%. r/w 0x00 pwm7_posedge 0x40 pwm mode: sets the positive edge of the output with respect to the period resolution. r/w 0x00 pwm7_negedge dac7_levelout 0x44 pwm mode: sets the negative edge of the output with respect to the period resolution. dac mode : sets the desired output level, from 0-100%. r/w 0x00 pwm8_posedge 0x48 pwm mode: sets the positive edge of the output with respect to the period resolution. r/w 0x00 table 1-3 corepwm register definitions (continued)
corepwm v4.1 register map 17 pwm8_negedge dac8_levelout 0x4c pwm mode: sets the negative edge of the output with respect to the period resolution. dac mode : sets the desired output level, from 0-100%. r/w 0x00 pwm9_posedge 0x50 pwm mode: sets the positive edge of the output with respect to the period resolution. r/w 0x00 pwm9_negedge dac9_levelout 0x54 pwm mode: sets the negative edge of the output with respect to the period resolution. dac mode : sets the desired output level, from 0-100%. r/w 0x00 pwm10_posedge 0x58 pwm mode: sets the positive edge of the output with respect to the period resolution. r/w 0x00 pwm10_negedge dac10_levelout 0x5c pwm mode: sets the negative edge of the output with respect to the period resolution. dac mode : sets the desired output level, from 0-100%. r/w 0x00 pwm11_posedge 0x60 pwm mode: sets the positive edge of the output with respect to the period resolution. r/w 0x00 pwm11_negedge dac11_levelout 0x64 pwm mode: sets the negative edge of the output with respect to the period resolution. dac mode : sets the desired output level, from 0-100%. r/w 0x00 pwm12_posedge 0x68 pwm mode: sets the positive edge of the output with respect to the period resolution. r/w 0x00 pwm12_negedge dac12_levelout 0x6c pwm mode: sets the negative edge of the output with respect to the period resolution. dac mode : sets the desired output level, from 0-100%. r/w 0x00 pwm13_posedge 0x70 pwm mode: sets the positive edge of the output with respect to the period resolution. r/w 0x00 pwm13_negedge dac13_levelout 0x74 pwm mode: sets the negative edge of the output with respect to the period resolution. dac mode : sets the desired output level, from 0-100%. r/w 0x00 pwm14_posedge 0x78 pwm mode: sets the positive edge of the output with respect to the period resolution. r/w 0x00 pwm14_negedge dac14_levelout 0x7c pwm mode: sets the negative edge of the output with respect to the period resolution. dac mode : sets the desired output level, from 0-100%. r/w 0x00 pwm15_posedge 0x80 pwm mode: sets the positive edge of the output with respect to the period resolution. r/w 0x00 pwm15_negedge dac15_levelout 0x84 pwm mode: sets the negative edge of the output with respect to the period resolution. dac mode : sets the desired output level, from 0-100%. r/w 0x00 pwm16_posedge 0x88 pwm mode: sets the positive edge of the output with respect to the period resolution. r/w 0x00 pwm16_negedge dac16_levelout 0x8c pwm mode: sets the negative edge of the output with respect to the period resolution. dac mode : sets the desired output level, from 0-100%. r/w 0x00 table 1-3 corepwm register definitions (continued)
design description corepwm v4.1 18 pwm_stretch 0x90 when 0, the state of pwmx is determined by pwmx_posedge/ negedge register settings. when 1, pwmx is set to pwm_stretch_valuex. r/w 0x0000 tachprescale 0x94 clock prescale setting. determines effective clock rate for the counter based on pclk: 0000 = divide by 1 (default) 0001 = divide by 2 0010 = divide by 4 0011 = divide by 8 0100 = divide by 16 0101 = divide by 32 0110 = divide by 64 0111 = divide by 128 1000 = divide by 256 1001 = divide by 512 1010 = divide by 1,024 1011 = divide by 2,048 others = divide by 2,048 r/w 0x0 tachstatus 0x98 tach status register which contains one bit per tach input, indicating whether the respective tachpulsedur register has been updated at least once since the bit was cleared. the bits in this register gets cleared by writing 1, 0 does not have any effect. r/ w1c 0x0000 tac h i rq m a s k 0 x 9 c tach interrupt mask register with one bit per tachometer signal, indicating whether corepwm needs to assert an interrupt if the respective bit in tachstatus register is asserted. r/w 0x0000 tachmode 0xa0 tach mode. sets the measurement mode used for each tach input. when 0: tach input is continuously measured and stored in the respective tachpulsedur register . when 1: a one-time measurement is performed only if the respective bit in tachstatus register is cleared. r/w 0x0000 tachpulsedur_0 0xa4 stores the number of timer ticks between two successive positive (or negative) edges from the tachin[0]. the edge to be used is configurable. if the number of timer ticks exceeds the maximum register value, the value of 0 shall be stored instead. r0x0000 tachpulsedur_1 0xa8 stores the number of timer ticks between two successive positive (or negative) edges from the tachin[1]. the edge to be used is configurable. if the number of timer ticks exceeds the maximum register value, the value of 0 shall be stored instead. r0x0000 tachpulsedur_2 0xac sstores the number of timer ticks between two successive positive (or negative) edges from the tachin[2]. the edge to be used is configurable. if the number of timer ticks exceeds the maximum register value, the value of 0 shall be stored instead. r0x0000 table 1-3 corepwm register definitions (continued)
corepwm v4.1 register map 19 tachpulsedur_3 0xb0 stores the number of timer ticks between two successive positive (or negative) edges from the tachin[3]. the edge to be used is configurable. if the number of timer ticks exceeds the maximum register value, the value of 0 shall be stored instead. r0x0000 tachpulsedur_4 0xb4 stores the number of timer ticks between two successive positive (or negative) edges from the tachin[4]. the edge to be used is configurable. if the number of timer ticks exceeds the maximum register value, the value of 0 shall be stored instead. r0x0000 tachpulsedur_5 0xb8 stores the number of timer ticks between two successive positive (or negative) edges from the tachin[5]. the edge to be used is configurable. if the number of timer ticks exceeds the maximum register value, the value of 0 shall be stored instead. r0x0000 tachpulsedur_6 0xbc stores the number of timer ticks between two successive positive (or negative) edges from the tachin[6]. the edge to be used is configurable. if the number of timer ticks exceeds the maximum register value, the value of 0 shall be stored instead. r0x0000 tachpulsedur_7 0xc0 stores the number of timer ticks between two successive positive (or negative) edges from the tachin[7]. the edge to be used is configurable. if the number of timer ticks exceeds the maximum register value, the value of 0 shall be stored instead. r0x0000 tachpulsedur_8 0xc4 stores the number of timer ticks between two successive positive (or negative) edges from the tachin[8]. the edge to be used is configurable. if the number of timer ticks exceeds the maximum register value, the value of 0 shall be stored instead. r0x0000 tachpulsedur_9 0xc8 stores the number of timer ticks between two successive positive (or negative) edges from the tachin[9]. the edge to be used is configurable. if the number of timer ticks exceeds the maximum register value, the value of 0 shall be stored instead. r0x0000 tachpulsedur_10 0xcc stores the number of timer ticks between two successive positive (or negative) edges from the tachin[10]. the edge to be used is configurable. if the number of timer ticks exceeds the maximum register value, the value of 0 shall be stored instead. r0x0000 tachpulsedur_11 0xd0 stores the number of timer ticks between two successive positive (or negative) edges from the tachin[11]. the edge to be used is configurable. if the number of timer ticks exceeds the maximum register value, the value of 0 shall be stored instead. r0x0000 tachpulsedur_12 0xd4 stores the number of timer ticks between two successive positive (or negative) edges from the tachin[12]. the edge to be used is configurable. if the number of timer ticks exceeds the maximum register value, the value of 0 shall be stored instead. r0x0000 tachpulsedur_13 0xd8 stores the number of timer ticks between two successive positive (or negative) edges from the tachin[13]. the edge to be used is configurable. if the number of timer ticks exceeds the maximum register value, the value of 0 shall be stored instead. r0x0000 tachpulsedur_14 0xdc stores the number of timer ticks between two successive positive (or negative) edges from the tachin[14]. the edge to be used is configurable. if the number of timer ticks exceeds the maximum register value, the value of 0 shall be stored instead. r0x0000 table 1-3 corepwm register definitions (continued)
design description corepwm v4.1 20 tachpulsedur_15 0xe0 stores the number of timer ticks between two successive positive (or negative) edges from the tachin[15]. the edge to be used is configurablle. if the number of timer ticks exceeds the maximum register value, the value of 0 shall be stored instead. r0x0000 note: 0d = decimal; 0x = hexi decimal; 0b = binary. table 1-3 corepwm register definitions (continued)
corepwm v4.1 configuration example 21 configuration example figure 1-3 demonstrates how several register configurations affect general purpose and low ripple dac pwm output waveform generation. figure 1-3 corepwm waveform generation example configuring the following registers using an 8-bit apb resolution will yield the example pwm waveforms below, based on a 25 mhz system clock = 40 ns system clock period: note: 0x = hexadecimal prescale = 0x1 period = 0x0d pwm_enable = 0x1f pwm1_posedge = 0x02 pwm1_negedge = 0x08 pwm2_posedge = 0x08 pwm2_negedge = 0x02 pwm3_posedge = 0x00 pwm3_negedge = 0x01 pwm4_posedge = 0x01 pwm4_negedge = 0x01 pwm period granularity = pwm_pg = clock period (prescale + 1) = 40 ns 2 = 80 ns pwm period = pwm_pg (period +1) = 80 ns 14 = 1.12 s enable pwm signals 1, 2, 3, 4, and 5. pwm1 and pwm2 duty cycle = 6/14 => 42.8% toggle pwm4 output (always 50% duty cycle) 25% duty cycle dac mode output, based on averaging by phase accumulator circuit pwm3 duty cycle => 7.1% prescale value of 1 = 2 system clock periods 34 25 1 0 pwm3 pwm4 pwm5 pwm2 13 pwm1 pclk 910 811 7 612 13 period value of 13 with prescale value of 1 = 14 2 system clock periods per pwm period 1 0 3 2 1 0 dac5_levelout = 0x3f low ripple dac mode uses phase accumulator to create an average density duty cycle. if the shadow register has been configured for this channel, then updates will occur at the beginning of the period. in either mode, using the shadow register with prescale/period allows for synchronized updates.
design description corepwm v4.1 22 figure 1-4 to figure 1-7 on page 23 demonstrate how to avoid overlapping of the dead banding issue using the register configurations of channel 1 and channel 2 as a pair. bo th channel 1(pwm1) and channe l 2(pwm2) are updated after writing a 1 to the sync_update configuration register to avoid overlapping of dead band space.. figure 1-4 dead band space example figure 1-5 center-aligned pwm waveform example dea d ban d s pa c e dea d ban d s pa c e 0 13 12 11 10 9 8 7 6 5 4 3 2 1 03 2 1 13 pwm2 pwm1 perio d value of 13 with pres c ale value of 1 = 14 2 system c lo c k perio d s per pwm perio d p c lk apb write pwm2_po s ed g e = 0x03 apb write pwm1_po s ed g e = 0x01 apb write pwm1_po s ed g e = 0x02 apb write pwm2_po s ed g e = 0x02 0 13 12 11 10 9 8 7 6 5 4 3 2 1 03 2 1 13 pwm1 perio d value of 13 with pres c ale value of 1 = 14 2 system c lo c k perio d s per pwm perio d p c lk apb write pwm1_po s ed g e = 0x03 apb write pwm1_ne g ed g e = 0x11
corepwm v4.1 configuration example 23 figure 1-6 left-aligned pwm waveform example figure 1-7 tach measurement 0 13 12 11 10 9 8 7 6 5 4 3 2 1 03 2 1 13 pwm1 period value of 13 with prescale value of 1 = 14 2 system clock periods per pwm period pclk apb write pwm1_posedge = 0x00 apb write pwm1_negedge = 0x06 pwm[0] period count 0123456701234567012345670123456701234567 change the value on pwm[0] based on pwm_stretch[0] tachstatus[0] start tach measurement tach count 0 1234567891011 12 tachint read tach count value tach measurement pwm_stretch[0] tachin[0] change the value on pwm[0] based on pwm_stretch[0] pwm_stretch_value = 1 pwm_stretch_value = 0
design description corepwm v4.1 24 apb interface timing figure 1-8 and figure 1-9 depict typical write cycle and read cycle timing relationships relative to the system clock. figure 1-8 data write cycle figure 1-9 data read cycle pclk psel pwrite penable paddr pwdata register address register write data pclk psel pwrite penable paddr prdata register address register read data
25 2 tool flows corepwm is licensed in two ways. depending on your license, tool flow func tionality may be limited. obfuscated complete rtl code is provided for the core, allowing the core to be instan tiated with smartdesign. simulation, synthesis, and layout can be performed within libe ro ide. the rtl code for the core is obfuscated 1 and some of the testbench source files are not provided. instead, they are precompiled into the compiled simulation library. rtl complete rtl source code is provided for the core and testbenches. smartdesign the core can be configured using the configuration gui wi thin smartdesign. an exampl e of configuring one channel for pwm mode operation is shown in figure 2-1 on page 26 . note the following in this example: ? number of pwm channels is 1. ? apb bit width and correspondin g pwm resolution is 8 bits. ? the prescale value (the number of clock ticks between period ti cks) is selected to be fixed at 64, reducing the tile count, as no registers are used. ? the period value is not fixed and hence software-controlled. ? the shadow update register is enabled, allowing for synchronized pwm updates at the beginning of the period count. ? the positive edge of the pwm is not fixed and hence software-controlled. ? the negative edge of the pwm waveform is fixed at period count 0. ? the user testbench is selected to be generated. 1. obfuscated means formatting and commen ts have been removed from the rtl source files, and all instance and net names have b een replaced with random character sequences.
tool flows corepwm v4.1 26 an example of configuring one channel fo r low ripple dac operation is shown in figure 2-2 on page 27 . note the following in this example: ? number of pwm channels is 1. ? apb bit width and corresponding pwm/dac resolution is 8 bits. ? the prescale and period values can be used in conjunction with the shadow update register to update dac1_levelout values at a given period. for example, 3 dacs could be updated simultaneously based on the prescale and period values if the shadow update register is enabled. in this example, the dac1_levelout value is updated whenever the apb bus updates the dac1_levelout register. ? the dac levelout value is not fixed and hence software-controlled. note the dac1_levelout value is synonymous with a duty cycle value; i.e., an 8-bit dac1_levelout hex value of 7f is equal to an average duty cycle of 50% and will yield half of the full analog value after rc filtering. ? note the fixed pwm posedge value does not apply to dac mode channel. ? the user testbench is selected to be generated. figure 2-1 corepwm configuratio n within smartdesign ? pwm mode
corepwm v4.1 importing into libero ide 27 importing into libero ide corepwm is available for do wnload to the smartdesign ip catalog, via the libero ide web repository. for information on using smartdesign to instantiate, configure, connect, and generate cores, refer to the libero ide online help. simulation flows to run simulations, select the user testbench within the smartdesign corepwm configurat ion gui, right-click, and select generate design . when smartdesign generates the de sign files, it will install the appropriate testbench files. set the design root to the corepwm instantiation in the libero ide design hierarchy pane, and click the simulation icon in the libero ide design flow window. this will invoke modelsim? and automatically run simulation. figure 2-2 corepwm configuration within smartdesign ? dac mode
tool flows corepwm v4.1 28 a simplified block diagram of the user testbench is shown in figure 2-3 . the user testbench instantiates the corepwm macro and provides a register write stimulus process, register read process, and a pwm output duty cycle check process. synthesis in the libero ide having set the design route appropriately, click the synthesis icon in libero ide. the synthesis window appears, displaying the synplicity? project. set synplicity to use the verilog 2001 standard if verilog is being used. to run synthesis, select the run icon. place-and-route in libero ide having set the design route appropriat ely and run synthesis, click on the layout icon in libero ide to invoke designer. corepwm requires no special place-and-route settings. figure 2-3 corepwm ve rification testbench user testbench register write stimulus register read checker corepwm pwm output checker
29 3 example applications for general purpose pwm applications, a duty cycle calculator is available online to assist in calculating the pwm posedge and negedge register values, given a requested duty cycle. this is provided on the actel website as a downloadable excel spreadsheet: http://www.actel.com/documents/duty_cycle_calc.zip for dac applications, a low ripple dac ca lculator is also available online: http://www.actel.com/documen ts/low_ripple_dac_calc.zip general purpose pwm applicat ion ? temperature monitor a typical temperature monitor application using corepwm is shown in figure 3-1 . in this example, fan speed is controlled by fluctuations in the ntc thermistors resistive va lue. as shown, changes in th e input voltage to the voltage monitor port will be converted to a digital value via the adc and forwarded to an on-chip microcontroller (such as core8051s). the microcontroller algorithm will periodically configure/reconfigure corepwm registers based on the thermistor value and/or the fans tachometer value. dac a typical dac application using corepwm is shown in figure 3-2 on page 30 . in this example, pwm output is averaged to a varying dc voltage. at reset, the pwm duty cy cle, or level out value, is 100% and the voltage increases to the rail of 12 volts. the pwm duty cycle / level out value changes to 75% and then 50%, and the output of the rc filter follows this by dropping to 8 volts and th en 6 volts. the generated ripple voltage is a function of the rc circuit values, the apb system clock period, and the pwm duty cycle. figure 3-1 temperature/voltage monitor application using corepwm in a fusion device fusion device corepwm osc microcontroller (core8051s) output pad coreai analog block (ab) adc analog mux quad analog block (voltage monitor port) +12 v 12 v, 4-wire fan pwm tach +5 v ntc thermistor 10k @ 25c 10k 1%
example applications corepwm v4.1 30 as shown, a field-effect transistor (fet ) is used to increase and decouple the output voltage/current from the fusion device. the load is monitored and changes to the pwm output are processed via a microcontroller (core8051s, coreabc, etc.). figure 3-2 dac application using corepwm in fusion device fusion device coreai analog block (ab) quad analog block (power mosfet gate driver port) corepwm osc microcontroller (core8051) adc quad analog block (voltage monitor port) +12 v analog mux r c load 12 v 8 v 6 v 3.3 v 100% 75% 50% pwm duty cycle: load output pwm output to fet 6 v 3.3 v time in general-purpose pwm mode, ripple voltage is a function of pwm duty cycle, pwm period, and the rc time constant. in low-ripple dac mode, pulse width is effectively reduced to 1 clock cycle period, significantly reducing the ripple at the output of a low pass filter.
corepwm v4.1 dac 31 the fet, in this case, is used to illustrate the ability to ex tend the dacs output to 12 v. for most applications, 3.3 v is sufficient. higher clock speeds (and therefore lower ripple) can be achieved by driving the rc filter with a general purpose ttl output. using low ripple dac mode has the added benefit of requiring a smaller time constant for the filter, which allows for smaller r and c components to be used. a low ripple dac calc ulator is available to assist in determining the ideal values for r and c.

33 4 software driver drivers for corepwm are available via the firmware catalog to ol provided with libero ide. for more information on the firmware catalog, refer to www.actel.com/products/software/firmwarecat/default.aspx .

35 5 list of document changes the following table lists critical changes that were made in the current version of the document. previous version changes in current version (5020113-1) page 5020113-1 updated core version to v4.1. n/a 5020113-0 updated utilization and performance tables. 6 C 9 added low-cost tachometer solution with up to 16 digital inputs. n/a added center-aligned pwm support. 22 updated tool flow to support libero ide v8.5 and smartdesign. 25 updated figure 1-3 , figure 1-5 , and figure 1-6 in the configuration example section . 21 , 22 , 23 updated figure 3-2 . 30 updated the software driver section. 33

37 a product support actel backs its products with various support services including customer service, a customer technical support center, a web site, an ftp site, electronic mail, and worldw ide sales offices. this append ix contains info rmation about contacting actel and usin g these support services. customer service contact customer service for non-technical product support , such as product pricing, product upgrades, update information, order status, and authorization. from northeast and north central u.s.a., call 650.318.4480 from southeast and southwest u.s.a., call 650. 318.4480 from south central u.s.a., call 650.318.4434 from northwest u.s.a., call 650.318.4434 from canada, call 650.318.4480 from europe, call 650.318.4252 or +44 (0) 1276 401 500 from japan, call 650.318.4743 from the rest of the world, call 650.318.4743 fax, from anywhere in the world 650.318.8044 actel customer technical support center actel staffs its customer technical support center with highly skilled engineers who can help answer your hardware, software, and design questions. the custo mer technical support center spends a gr eat deal of time creating application notes and answers to faqs. so, before you contact us, please visi t our online resources. it is very likely we have already answered your questions. actel technical support visit the actel customer support website ( www.actel.com/custsup/search.html ) for more information and support. many answers available on the searchable web resource includ e diagrams, illustrations, and links to other resources on the actel web site. website you can browse a variety of technical and non-technical information on actels home page , at www.actel.com . contacting the customer technical support center highly skilled engineers staff the technical support center from 7:00 a . m . to 6:00 p . m ., pacific time, monday through friday. several ways of co ntacting the center follow: email you can communicate your technical questions to our email address and receive answers back by email, fax, or phone. also, if you have design problems, you can email your design files to receive assistance. we constantly monitor the email account throughout the day. when sending your request to us, please be sure to include your full name, company name, and your contact information for effi cient processing of your request. the technical support email address is tech@actel.com .
product support corepwm v4.1 38 phone our technical support center answers all calls. the center re trieves information, such as your name, company name, phone number and your question, and then issues a case number. the center then forwards the information to a queue where the first available application engineer receives the data and returns your call. the phone hours are from 7:00 a . m . to 6:00 p . m ., pacific time, monday through friday. the technical support numbers are: 650.318.4460 800.262.1060 customers needing assistance outside the us time zones can either contact technical support via email ( tech@actel.com ) or contact a local sales office. sales office listings can be found at www.actel.com/contact/offices/index.html .
39 a actel electronic mail 37 telephone 38 web-based technical support 37 website 37 apb interface timing 24 applications 29 c configuration examples 21 contacting actel customer service 37 electronic mail 37 telephone 38 web-based technical support 37 corepwm key features 5 version 6 customer service 37 d dac 29 e example 1 channel for low ripple dac 26 dac application 30 temperature monitor 29 f functional blocks 11 i importing into libero ide 27 m modes general purpose pwm 11 low ripple dac 11 o overview 5 p parameters, verilog and vhdl 14 place-and-route 28 port signals 12 product support 37 ? 38 customer service 37 electronic mail 37 technical support 37 telephone 38 website 37 r register map 15 s simulation 27 simulation flows 27 smartdesign 25 software driver 33 supported interfaces 6 synthesis 28 t technical support 37 tool flows 25 importing into libero ide 27 simulation 27 smartdesign 25 u utilization and performance 6 w web-based technical support 37 index
actel corporation ? 2061 stierlin court ? mountain view, ca 94043 ? usa phone 650.318.4200 ? fax 650.318.4600 ? customer service: 6 50.318.1010 ? customer applications center: 800.262.1060 actel europe ltd . ? river court, meadows business park ? station approach, blackwater ? camb erley surrey gu17 9ab ? united kingdom phone +44 (0) 1276 609 300 ? fax +44 (0) 1276 607 540 actel japan ? exos ebisu building 4f ? 1-24-14 ebisu shibuya-ku ? tokyo 150 ? japan phone +81.03.3445.7671 ? fax +81.03.3445.7668 ? http://jp.actel.com actel hong kong ? room 2107, china resources building ? 26 harbour road ? wanchai ? hong kong phone +852 2185 6460 ? fax +852 2185 6488 ? www.actel.com.cn 50200113-2/2.10 actel is the leader in low-power and mixed-signal fpgas and offers the most comprehensive portfolio of system and power management solutions. power matters. learn more at www.actel.com.

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